The present invention relates to an underfill preform and, in particular, to an adhesive underfill preform and to electronic devices including an adhesive underfill.
Since the invention of integrated circuits in early 1960""s, their use has proliferated and they have become indispensable to the multitude of electronic products that modem society has come to rely on and take for granted. While there are many methods of packaging circuits and other semiconductor chips into functional form, their usefulness is greatly enhanced if the physical size of such packaged electronic devices is small and the cost of such packaged devices is low.
Traditionally, connections to semiconductors are made with fine gold or aluminum bond wires that loop from contact pads arranged around the periphery of the top surface of the semiconductor chip (i.e. the side of the chip on which the electronic circuit has been formed) to a lead-frame, header or other package or substrate to which the bottom surface of the semiconductor chip is attached. The technology of bond wire interconnection has been perfected to such a degree that the cost of each bond wire connection is less than one cent ($0.01 U.S.). The electrical characteristics of thin bond wires looping even over a relatively short distance necessarily introduce unwanted inductance and capacitance into the interconnection and thus reduce the bandwidth and operating rate of the electronic devices. This limitation has become more significant in recent years as a result of the development of much faster microprocessors and higher frequency signal processing and communication devices.
One way to reduce the capacitance and inductance of these interconnections is to shorten the length of the interconnection path. One effective conventional way to accomplish this is by flipping the semiconductor chip over (thus, the appellation xe2x80x9cflip chipxe2x80x9d) so that the contact pads are immediately adjacent to the substrate built on which are formed a corresponding set of contact pads to which the contact pads of the semiconductor may be joined directly. U.S. Pat. No. 3,429,040 entitled xe2x80x9cMethod of Joining a Component to a Substratexe2x80x9d issued to L. F. Miller describes a flip chip arrangement in which the semiconductor chip is attached to the substrate by solder bumps. The distance between the flip chip and the substrate has been reduced to about 50-100 microns and thereby to enable operation at dramatically higher frequencies.
There are many conventional ways of depositing solder or conductive adhesives for the bonding of electronic components and flip chip semiconductor devices to substrates, such as those set forth, for example in U.S. Pat. No. 3,401,126 entitled xe2x80x9cMethod of Rendering Noble Metal Conductive Composition Non-Wettable by Solderxe2x80x9d, U.S. Pat. No. 3,429,040 entitled xe2x80x9cMethod of Joining a Component to a Substratexe2x80x9d, U.S. Pat. No. 4,113,981 entitled xe2x80x9cElectrically Conductive Adhesive Connecting Arrays of Conductorsxe2x80x99, U.S. Pat. No. 5,074,947 entitled xe2x80x9cFlip-Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d, U.S. Pat. No. 5,196,371 entitled xe2x80x9cFlip Chip Bonding Method Using Electrically Conductive Polymer Bumpsxe2x80x9d, U.S. Pat. No. 5,237,130 entitled xe2x80x9cFlip Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d, and U.S. Pat. No. 5,611,140 entitled xe2x80x9cMethod of Forming Electrically Conductive Polymer Interconnects on electrical Substratesxe2x80x9d. One problem common to these prior art techniques is that they all require operations that are substantially different from those normally associated with semiconductor fabrication. As a result, a substantially different kind of process is being employed and a new business has evolved in which service companies perform solder deposition onto semiconductor wafers as well as adhesive deposition onto such wafers.
The interconnection of semiconductor devices in flip chip configuration has evolved from the use of very elaborate metallization and metallurgy to form a conductive bump of suitable height to which connection may be made, to the use of a less demanding and inexpensive solder bump. Soldering and solder-bump technology and metallurgy may be changed in known manner to accommodate changes in composition and methods of depositions suitable for lower and higher temperature reflow soldering of such interconnections. The inherent limitation of solder bump technology has become apparent when semiconductor devices are sought to be directly attached to an organic substrate due to the differences in the coefficient of thermal expansion (CTE) of the materials. For example, FR-4 fiberglass substrates have a CTE of 17 ppm/xc2x0 C. whereas the semiconductor chip has a CTE of 3 ppm/xc2x0 C. Substantial limitations similarly arise when the size of the semiconductor chip is greater than five millimeters (5 mm) on each edge, even when the flip chip interconnection is made to an alumina substrate which has a CTE of only 7 ppm/xc2x0 C. The solder joints have a modulus of elasticity of about 10,000,000 psi and so have very little compliance, thereby rendering the solder connections subject to fatigue failures when subjected to cyclical temperature excursions.
Alternatives to solder-based interconnections have been employed. U.S. Pat. No. 4,113,981 entitled xe2x80x9cElectrically Conductive Adhesive Connecting Arrays of Conductorsxe2x80x9d issued to Fujita et al. describes a non-conductive adhesive base that is filled with too few conductive particles to render it conductive, except where it may be compressed. Fujita et al. describes using such adhesive to attach raised contacts where normally non-contacting conductive particles in the non-conductive adhesive are pressed against raised contacts of a device so that the raised contacts of the device are in electrical contact with the raised contact pads of the substrate and where isolation between laterally adjacent contacts is maintained by the insulating resin. In a conventional semiconductor wafer, the contact pads, normally formed of aluminum, are recessed below the final insulating inorganic passivation layer. One of the limitations of the Fujita patent is that the contact pads must extend above the top of the insulating passivation layer or substrate. This additional preparation, either as part of the semiconductor wafer fabrication or as a separate process, tends to increase the cost of the semiconductor device and, therefore, the interconnection. Another limitation of the Fujita interconnection is that only a limited number of conductive paths may be formed within each conductive contact, so that electrical isolation between only a few of the conductor particles can render the interconnection non-conductive, and, therefore, useless.
Isotopically conductive adhesives have long been used for bonding the backside of the semiconductor die to a package before the contact pads of the die are wire-bonded to the package leads and have also found extensive use to attach semiconductor components, chip resistors and chip capacitors in hybrid circuit assemblies and in printed wiring board assemblies. But conductive adhesive connections also impose requirements on the semiconductor wafer fabricators and on circuit board manufacturers that may differ from their normal processing.
An early usage of conductive adhesive for flip chip bonding is suggested by Scharf et al. in an article entitled xe2x80x9cFlip-Component Technologyxe2x80x9d, published in the Proceedings of IEEE Electronic Component Conference, 1967 (pp. 269-275). Therein, conductive adhesive bumps were stenciled onto a substrate having an array of sixteen bond pads for each semiconductor die that was to be bonded. Scharf et al. focus on how to create a better stencil for printing precision bumps and state certain advantages of using conductive adhesive, such as lower temperature bonding and lower cost. Subsequently, U.S. Pat. No. 4,442,966, entitled xe2x80x9cMethod of Simultaneously Manufacturing Multiple Electrical Connections Between Two Electrical Elementsxe2x80x9d issued to P. Jourdain et al. describes the use of conductive paste for bonding aluminum pads on a semiconductor to a substrate in which the stenciling method of depositing the conductive adhesive bumps on the contact pads is employed and in which pressure and heat are applied during assembly of the semiconductor to the substrate.
The uses of such conductive epoxy adhesives for bonding semiconductor chips and the application of such adhesives have been reported in several articles, such as by K. Gilleo in xe2x80x9cDirect Chip Interconnect Using Polymer Bondingxe2x80x9d, 39th Electronic Component Conference, May 1989, (pp.37-44) and U.S. Patents. The limitations of rigid conductive adhesives therein are similar to those of the solder bump approaches, i.e. the connections tend to fracture under temperature cycling. The adhesive joints in the reported applications employ rigid adhesives having a modulus of elasticity of 1,000,000 psi or higher and, as a result, have very little compliance and are subject to delamination or fracture failures over repeated temperature excursions.
Thus, the major problem facing chip to component or chip to board interconnection is the internal stress arising from the difference between the coefficient of thermal expansion of the silicon of the semiconductor chip and that of the next level board, i.e. the substrate to which the semiconductor chip is attached. Both conventional conductive adhesives and solder-bump technologies are hampered by these high-stress-related failures which are exacerbated by extreme temperature differences and larger chips, as is the trend for modern electronics.
One possible solution to this technological stress problem is to engineer the next level board, i.e. the substrate, to have the same coefficient of thermal expansion as that of the semiconductor chip, e.g., about 3 ppm/xc2x0 C. While this technical approach has been successfully utilized by some, it is not used extensively because of the undesirable higher cost to both develop and manufacture such a substrate and to create the infrastructure necessary to support such new technology. Even more vexing is the fact that the lowest cost common electronic substrate is a fiberglass laminate with epoxy resin, such as FR-4, which is commonly used in printed wiring circuit boards and which has a CTE of 17 ppm/xc2x0 C. Conventional commercial electronic equipment almost universally employs FR-4 printed circuit boards. Thus, either an extra intermediate substrate would be required, at added cost, or a specialized substrate material to replace FR-4 would be required. The basic problem remains.
The conventional solution to the stress problem is to seek to spread out the stress using an epoxy underfill dispensed into the space between the semiconductor chip and the substrate that does not contain conductive connections. While properly dispensed underfill does in many cases help to increase the number of thermal cycles that such interconnections can survive by a factor of 6-8, depending on semiconductor die size and the temperature excursions, the inherent problem of balancing the beneficial compressive stress of the high-strength underfill that limits the cycling strain achieved against the devastating shear stress that will delaminate or break the joints or parts remains. Every increase in the dimension of the semiconductor die increases the shear stress, and thus the reliability of the assembled flip chip under thermal cycling must be re-evaluated for each particular range of temperatures. Similarly, when the extreme of a temperature excursion is extended to lower or higher temperature, additional shear stress can adversely affect the reliability of the assembled flip chip, also necessitating expensive re-evaluation testing. While dispensing suitable high-modulus of elasticity underfill can help to increase the ability of the flip chip device assembly to withstand thermal excursion stresses, nevertheless it is limited in terms of both the size of semiconductor device that can be utilized and the differential between the thermal expansion coefficient of expansion of the semiconductor chip and that of the next level substrate. Moreover, at least part of the difficulty with dispensed underfill arises from inconsistent dispensing, incomplete underfill, and voids.
Further, U.S. Pat. No. 5,667,884 entitled xe2x80x9cArea Bonding Conductive Adhesive Preformsxe2x80x9d issued to Bolger describes sheet preforms for conductive adhesive interconnections, not solder connections. Bolger""s preforms comprise a multiplicity of electrically conductive adhesive members, each being separated from the other by a non-electrically conductive adhesive, and being useful in the assembly of multi-chip modules and other electronic devices. Resins generally suitable according to Bolger include high Tg thermoplastic and thermosetting polymers that cure at greater than 120xc2x0 C. and have a glass transition temperature Tg greater than about 70xc2x0 C. (column 8, lines 33-46). The adhesive in Bolger""s examples I-III, for example, is novolac epoxy resin that forms a relatively rigid adhesive having a Tg which is typically over 150xc2x0 C. and a modulus of elasticity of over 106 psi, i.e. over one million psi (column 7, lines 46-55). The sheet preforms as described in the Bolger patent, however, appear to remain on the release film on which they are formed until they are attached to an individual semiconductor component or a substrate, perhaps because they may lack dimensional stability if separated therefrom. In addition, Bolger""s sheet preforms also have several other undesirable, and perhaps more important, limitations. First, Bolger requires that the conical or domed conductive adhesive elements extend above the surface of the non-conductive adhesive, generally having a height in the range of 125%-225%, and preferably about 150%-200%, of the thickness of the surrounding non-conductive adhesive, while also being less than 150% of its diameter (column 7, lines 8-15). This requirement of Bolger would render making proper interconnections difficult or impossible to achieve with solder which naturally takes on a spherical domed shape. In fact, it appears from Bolger""s repetition of the point to be of great importance that care be taken to avoid covering the tops of previously formed conductive adhesive members with the non-conductive adhesive composition (column 12, lines 31-46).
A membrane having a pattern of conductive pads within an insulating matrix employing a high strength adhesive system having a high modulus of elasticity is reported by R. W. Johnson, et. al. xe2x80x9cAdhesive Based Flip Chip Technology for Assembly on Polyimide Flex Substratesxe2x80x9d, International Conference on Multichip Modules, (April, 1997). One problem with the approach reported by Johnson et. al. is that their conventional rigid resin system having a high modulus of elasticity, such as a novolac epoxy base resin, cannot accommodate the substantial differences between the coefficients of thermal expansion (CTE) of semiconductor dies or chips and of substrate materials, such as FR4, ceramic and other common rigid substrate materials commonly employed, over the range of thermal temperatures typically specified and/or experienced. The approach of Johnson et al. to employ a flexible substrate that is capable of yielding or flexing may not be compatible with many applications, especially certain computer, telecommunication aerospace and defense applications. An alternate approach of engineering a customized substrate material that closely matches of the electronic components that will be attached thereto is both too expensive for many applications and impractical where the electronic components themselves have a substantially different CTE. In most applications, however, one must eventually connect to an FR4 printed circuit wiring board that has a high CTE of about 17 ppm/xc2x0 C.
Inherent in all of the foregoing, even in the case of a substrate with its CTE matched to the chip, when the device becomes substantially large, there is still inherent stress caused by of the mismatch between the CTE of the solder or adhesive, typically in the range of about 25 ppm/xc2x0 C. to over 40 ppm/xc2x0 C., in comparison to the CTE of 3 ppm/xc2x0 C. for the silicon chip and 17 ppm/xc2x0 C. for the FR4 printed wiring circuit board. In order to reduce the strain involved in the solder joints during the thermal excursion from the xe2x80x9czeroxe2x80x9d stress point of soldering, a dispensed underfill having high rigidity is conventionally used to control the strain involved within the solder conductor columns.
Almost all of the underfill materials used today are liquid epoxies filled with quartz and other insulating particulates to control its CTE to as low a value as possible. These liquid epoxy encapsulants are dispensed around the perimeter of the device, such as a semiconductor chip, after the device assembled to and interconnected with a substrate. In the case of soldered flip chips, such as are commonly called xe2x80x9cC4xe2x80x9d connections (i.e. Controlled Collapse Chip Connections), the solder interconnections are made by a suitable solder reflow process. If soldering flux is used, it is then removed with a suitable solvent and the device is dried. The liquid encapsulants are intended to be pulled in by capillary action to fill in the space between the flip chip and the substrate not occupied by the solder columns during a curing cycle at high temperature. How well the encapsulant fills the spaces by capillary action before it cures is a strong determinant of the reliability of such device.
However, the high rigidity of the encapsulant also produces high internal stress and also tends to cause delamination under thermal and power cycling. To reduce the tendency to fracture-induced failure, fracture-capturing rubber or soft-phase structures are incorporated and dispersed inside the resin. Because dispensed liquid encapsulants often require a longer time to cure and are difficult to utilize in high-volume applications, there is a need for better formulated products to replace conventional liquid underfill.
While a preferred solution to the stress problem is found in electronic devices employing the flexible adhesive connections described in U.S. patent application Ser. No. 09/166,633 entitled xe2x80x9cFlip Chip Devices With Flexible Conductive Adhesive,xe2x80x9d there remains a need for solder-based interconnections in certain applications, for example, existing electronic devices where the expense or time that would be required to replace the solder-based interconnections is prohibitive or unavailable. In these applications in particular, there is a need for a more reliable and cost effective solution to the stress problem than is provided by dispensed underfill.
Another consideration in attaching semiconductor and other flip-chip components to a substrate is that of obtaining and maintaining intimate interfacial contact between the component and the substrate so that there will be adequate thermal energy transfer which leads to lower temperature operation and to greater reliability. Good thermal conductivity will not be obtained where air, voids or other foreign matter is trapped between the chip and the substrate, and is particularly difficult to obtain where a conventional patterned membrane of conductive and insulating organic polymer adhesive is employed. If a non-flowing dielectric underfill material is used, such as an epoxy of the sort described in U.S. Pat. No. 5,074,947 entitled xe2x80x9cFlip-Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d issued to Estes et al., voids will almost always form along the interface and thus, poor thermal conductivity will result across the interface between the electronic component and the substrate. In addition, if a rigid, non-flowing conductive adhesive of the sort described in the Estes et al. patent is used, the conductive adhesive will be subject to delamination and fracture failures under thermal stress and the interconnections formed thereby will be unreliable; the non-adhering dielectric underfill will not relieve the strain on the conductive adhesive and truly improve the aforementioned reliability.
Accordingly, there is a need for a rigid insulating adhesive underfill preform suitable for use with solder-based interconnections. It is desirable that such preform have high flow so as to reduce the size and incidence of voids and is further desirable that such preform may be employed with a plurality of devices or substrates formed on a single wafer or panel, respectively, which wafer or panel is separated into individual devices or substrates after the insulating preform is applied thereto.
To this end, the present invention comprises a rigid adhesive underfill preform for a substrate having a pattern of contact sites thereon and to include solder bumps comprising: a layer of adhesive material having a pattern of holes therethrough corresponding to the pattern of contact sites of the substrate, the layer of adhesive material having a thickness substantially similar to a height of the solder bumps, and wherein the adhesive material is rigid when cured and has a flow index greater than about 1.2.
According to another aspect of the present invention, a method of making an underfill preform having a pattern of holes therethrough comprises:
obtaining a mold plate having a substantially flat surface;
forming on the substantially flat surface a pattern of raised features having a height and corresponding to the pattern of holes;
depositing a layer of adhesive onto the substantially flat surface;
drying the layer of adhesive; and
removing the dried layer of adhesive from the substantially flat surface of the mold.